The disclosed invention generally relates to integrated circuit processing of silicon contacts, and is more particularly directed to a process for forming a multi-layer, low resistance diffusion barrier on silicon contacts which requires only one annealing procedure and can be achieved in a chemical vapor deposition reactor without potentially contaminating and time consuming removal therefrom.
The integrated circuit processing industry has recognized the advantages of forming diffusion barriers of low resistivity on silicon contacts. This permits shallower diffusions, and further allows lowering of the sheet resistance of polysilicon gates. Further, aluminum spiking, the diffusion of the aluminum contact into the silicon under high current and/or high temperature conditions, is also prevented or significantly reduced.
Known techniques for forming diffusion barriers on silicon contacts include techniques for forming a stacked titanium nitride/titanium silicide layer, as specifically shown in U.S. Pat. No. 4,690,730, issued to Tang et al. on Sept. 1, 1987, and assigned to Texas Instruments Incorporated.
While the techniques disclosed in U.S. Pat. No. 4,690,730 achieve a diffusion barrier of low resistivity, important considerations include the following. The processing is not self-aligned, and moreover requires more than one annealing step. Further, the process does not allow nitridation and silicidation to be achieved in the same reactor without removal of the wafer in process for other intermediate processing.